This invention relates generally to logic circuits that are used to perform computationally intensive tasks. More particularly, this invention relates to a hybrid logic circuit that is useful for computationally intensive tasks, such as wireless communications.
Programmable logic devices are widely used in the electronics industry. Conventional programmable logic devices typically comprise a general-purpose logic array and general-purpose interconnect. The typical logic array in general-purpose Field Programmable Gate Arrays (FPGAs) is designed to accommodate some random/control logic functionality and some structured/datapath logic functionality. Using FPGAs can be very inefficient when the programmed logic function comprises many datapath functions. Inefficient device utilization and performance degradation result when general-purpose random/control logic and routing resources are used for structured datapath functions. The more general-purpose the device architecture, the greater the inefficiency and performance degradation incurred by structured datapath functions.
In view of the foregoing, it would be highly desirable to provide a programmable architecture that improved the performance of structured datapath functions and improved device utilization efficiency.
A programmable datapath arithmetic array includes resources that are data buses connected to a matrix of data arithmetic units including fixed function units and programmable function units. In an exemplary embodiment, the programmable datapath arithmetic array includes only fixed function units. In another exemplary embodiment, the programmable datapath arithmetic array includes only programmable function units. Bidirectional interconnect is positioned between the data buses and the matrix of data arithmetic units to facilitate dynamic reconfiguration and operability of the programmable datapath arithmetic array.
Unlike field programmable gate arrays (FPGAs), the programmable datapath arithmetic array includes two organized logic resources, namely, datapath slices and datapath structures. In an exemplary embodiment, the programmable datapath arithmetic array comprises an array of datapath slices. For example, when the programmable datapath arithmetic array is a 1xc3x97N array, N represents the number of datapath slices. A datapath slice comprises an array of datapath structures. In an exemplary embodiment, if a datapath slice is a 1xc3x97M array, M represents the number of datapath structures. A datapath structure comprises an array of bit-slice blocks. In an exemplary embodiment, if a datapath structure is a 1xc3x97L array, L represents the number of bit-slice blocks. Bit-slice blocks comprise building blocks of the programmable datapath arithmetic array. A bit-slice block comprises a bit-specific portion and a common-control portion. In an exemplary embodiment, the programmable datapath arithmetic array comprises two types of datapath structures, namely fixed and re-programmable datapath structures. Fixed datapath structures implement a limited set of functions whereas re-programmable datapath structures implement a relatively larger set of functions.
The programmable datapath arithmetic array includes dedicated routing resources. Further, in a preferred embodiment, the programmable datapath arithmetic array comprises coarse-grained logic. In an exemplary embodiment, the programmable datapath arithmetic array is designed to facilitate and accelerate datapath functions. Examples of datapath functions are counters, incrementers, decrementers, shifters, scalers, adders, subtractors, accumulators, and decumulators. In an exemplary embodiment, datapath functions exhibit a uniformity of structure across all bits.